1. Field of the Invention
The present invention relates to a wafer level encapsulation chip and encapsulation chip manufacturing method and, more particularly, to a wafer level encapsulation chip and encapsulation chip manufacturing method capable of minimizing damages to a chip and preventing introduction of moisture into the inside of the chip upon chip handling by encapsulation through passivation on predetermined areas over the wafer-level packaging chip and predetermined areas of sides of the packaging chip.
2. Description of the Related Art
The electronic packaging chip widely used in various electronic products can be easily damaged due to external shocks since it has a minute electronic circuit therein. Thus, in the packaging chip manufacturing process, the packaging process is accompanied by hermetical sealing for overcoming external shocks and for formation of physical functions and a shape.
In particular, wafer-level packaging is necessary to meet the trend of recent electronic products such as compactness, high-performance, and so on. In general, a protection cap is bonded in a certain shape for wafer-level packaging (WLP) to a wafer with a circuit module mounted.
Meanwhile, the packaging chip is externally supplied with a signal and performs a specific operation. Thus, the packaging is required in a form enabling the external signal to be inputted to the inside of an electronic circuit.
FIG. 1 is a vertical cross-sectional view for showing a structure of a conventional packaging chip by wafer-level dicing.
In FIG. 1, the conventional packaging chip has a device substrate 10, a circuit module 20, a protection cap 30, a cavity 40, a connection layer 51, a bonding layer 52, vias 60, a connection pad 71, a bonding pad 72, and electrodes 80.
The device substrate 10 is formed of a semiconductor wafer on which a circuit module 20 is mounted. The circuit module 20 comprises a RF circuit module with a filter function.
The protection cap 30 is a wafer for protecting the circuit module 20. The cavity 40 is an empty space formed between the device substrate 10 and the protection cap 30 to accommodate the circuit module 20. Thus, the bonding pad 72 and the bonding layer 52 bond the protection cap 30 and the device substrate 10 in order for the circuit module 20 to be located inside the cavity 40.
The vias 60 are formed through the protection cap 30 so that an external signal and the circuit module 20 are electrically connected.
The connection pad 71 deposited below the vias 60 is connected to the connection layer 51. The electrodes 80 are electrically connected to the vias 60 on the upper surface of the protection cap 30.
Thus, an externally applied electric signal is sent to the internal circuit module 20 through the electrodes 80, the vias 60, the connection pad 71, and the connection layer 51.
FIGS. 2A to 2B are vertical cross-sectioned views for explaining a conventional dicing process.
FIG. 2A is a vertical cross-sectional view for showing two bonded wafers, that is, an lower wafer for the device substrate 10 and a upper wafer for the protection cap 30, prior to dicing.
The dotted lines in FIG. 2A indicate an area for dicing. FIG. 2B is a vertical cross-sectional view for showing a final packaging chip after the full dicing along the dotted lines shown in FIG. 2A.
The conventional dicing method vertically cuts a packaging chip by a dicing saw fully dicing at a time.
In general, the protection cap 30 is grabbed when the packaging chip is handled. Since the chip has a poor durability, there is a problem of damages to the chip due to a chipping phenomenon when the chip is handled.
Since there exists a thermal expansion coefficient difference between the vias 60 and the protection cap 30, there occurs a gap between the vias 60 and the electrodes 80. Moisture is introduced through the gap. Further, moisture is introduced into a gap between the bonding layer 52 and the bonding pad 72 and a gap between the bonding layer 52 and the device substrate 10 on sides of the packaging chip. Thus, there exists a problem of degrading a function of the circuit inside the chip.